1. Technical Field
Embodiments of the invention are generally related to operation of a memory device, and more particularly, but not exclusively, to a communication exchange between a memory device and a memory controller.
2. Background Art
In computer memory systems, such as those complying with the LPDDR3 standard JESD209-3 of the Joint Electron Devices Engineering Council (JEDEC), communications are exchanged between a memory controller and one or more memory devices via a command/address bus. The term “command/address” (also “CA” or “C/A”) refers to the characteristic of supporting or otherwise including either or both of command information and address information. LPDDR3 is one example of a standard which provides for training of a CA bus, which aids in compensating signal skew and other such impediments to communication between a memory controller and a memory device. CA bus training helps to assure that such communication is in compliance with timing requirements of the LPDDR3 standard.
Currently, LPDDR3 provides for sending an individual command over two transitions of a data clock. A first portion of such a command is sent via the CA bus on a rising transition of the data clock and a second portion of the command is sent via the CA bus on the falling transition of the data clock. This type of transfer timing is referred to as double data rate (DDR).
The burden imposed by implementing DDR increases as successive generations of memory system technology continue to push toward faster operating speeds, including faster data clock rates. Moreover, these successive generations increasingly implement efficiency mechanisms which rely on more frequent transitions into deeper power saving states. Recovery from such states often requires additional CA bus training The requirements of CA bus training are at cross-purposes with the trend toward faster operating speeds, deeper power saving states, and more frequent transitions into and out of such power saving states. Accordingly, implementing CA bus training in next-generation memory systems is increasingly challenging.